The present invention relates to a semiconductor device and a technique for manufacturing the same, and in particular relates to the structure of a field effect transistor which achieves an increase in the speed by utilizing the strain in a channel, and to the techniques effectively applied to the manufacturing of the field effect transistor.
One of the techniques for achieving a further increase in the speed of a CMIS (Complementary Metal Insulator Semiconductor) device is a strained silicon (Si) technique. This is a technique capable of achieving the improvement in the carrier mobility by applying a strain to a silicon layer. That is, if the silicon crystal lattice in a channel is strained by applying a stress to the channel, the symmetry of the band structure of the isotropic silicon crystal is broken, resulting in splitting in energy levels. As a result of the change of the band structure of the silicon crystal, the carrier scattering due to lattice vibration decreases or the effective mass decreases and so on, which improves the mobility of electrons and holes.
The examples of the strained silicon technique include a method of forming a Si:C layer, in which a part of the crystal lattice of silicon (Si) is substituted by carbon (C), in a source/drain (hereinafter, this source/drain is referred to as the Si:C source/drain), a method of forming a source/drain from a crystallized mixture made by forming a solid solution with a predetermined amount of germanium (Ge) into silicon (Si) (hereinafter, this source/drain is referred to as the embedded SiGe source/drain), SMT (Stress Memorization Technique), and DSL (Dual Stress Liner), some of which are already applied to commercial products.
The Si:C source/drain is formed by the strained silicon technique applied to an n-channel field effect transistor. The example of the strained silicon technique include a method of forming the Si:C layer by CVD (Chemical Vapor Deposition) (see Non-Patent Document 1 (B. Yang, “High-performance nMOSFET with in-situ Phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor”, in IEDM Tech. Dig, 2008, pp. 51-55)), and a method of forming the Si:C layer by ion-implanting carbon in forming an impurity diffusion layer constituting the source/drain (see Patent Document 1 (US Patent Application Publication 2007-0254461), and Non-Patent Document 2 (S. S. Chung, “Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor (Si:C S/D-E)”, in Symp. VLSI Tech. Dig., 2009, pp. 158-159)).